On Wed, Jul 6, 2011 at 11:57 AM, Patrick Doyle <wpdster@gmail.com> wrote:
> Before I go too far down this path, I figured I should just ask the question...
>
> The SDCLK<0> output pin on the PXA270 is wired to SA_SDCLK0, which is
> wired to pin Y11 on the FPGA.  I would like to run some synchronous
> logic (specifically, a dual clocked FIFO) off of this clock.  Right
> now, it doesn't seem to be wiggling.  I can think of 2 reasons
> immediately why I might not see it wiggling:
>
> 1) I did something wrong.
>
> 2) It doesn't wiggle unless it is configured to do so, and the default
> kernel doesn't configure it to wiggle.
>
> I'm working on trying to figure out option (1).  I thought I should
> ask you folks about option (2).
>
It seems like I need to set the K0FREE bit of the MDREFR register.  I
can do that fairly easily and hackilly by just OR-ing MDREFR_K0FREE
into MDREFR inside a loadable kernel module.

Is there a better (kernel or even user space) API for examining and
manipulating bits in MDREFR and other registers?

--wpd