On 02/04/16 00:33, Jens Rudberg wrote:
> The only work left to be done is a good implementation of the ecc
> calculation.
> Before implementing ecc calculation in the nand backend myself I wonder
> if there is a standard way that yaffs2 can do it.

Your choice of ECC is really down to your NAND part. The data sheet 
should tell you in terms of what number of bit errors may occur within a 
certain number of data bits. If your hardware design isn't locked down, 
you may need to err on the side of caution.

Back in the day, Toshiba contributed a software ECC algorithm to the 
Linux kernel which was sufficiently generic (and GPL+LibraryException 
licensed) that a lot of people adopted it as the last word in ECC. I 
believe it was good for many/most SLC parts, but not for many MLC.

There's a faster version of the same algorithm in yaffs_ecc.c.

> The param.use_nand_ecc that triggers a built in ecc function but this is
> limited to 512 bytes page size, correct?

use_nand_ecc is only used in yaffs1 mode, which only supports 512 byte 
pages (which YAFFS calls chunks).

In yaffs2 mode, param.no_tags_ecc comes into play. That causes YAFFS to 
apply essentially the same algorithm to the page, but extends it to 
cover any size.

In both cases, if the bit is set, the NAND layer is responsible for ECC; 
if cleared, YAFFS does it.


Ross